7 Concluding Remarks

merge latch latch merge RS data mux in1 in2 out Figure 19: Implementation of the Asynchronous Multiplexor produces the acknowledgements for storage aw1/aw2. The delay assumption (resulting from the chosen control input of the DW) in this implementation is that the delay of the storage (in areg) is less than the delay of the DW plus the environment delay between the acknowledgement and the read signal r1/r2. The production of Di,ari is simply a bundling of the data output of areg with the read signal ri. The SCPP-A design problem is to design the stages of a simplified Sproull Counterflow Pipeline Processor, through which results and instructions should flow in opposite direction as fast as possible. Each instruction–result pair must, however, meet in some stage and then interact with the corresponding processor. This paper discusses the design of asynchronous implementations for the SCPP-A, starting from the formulation of the communication behaviors of the high-level components down to the implementation of the basic components. Throughout the design, the main objective has been to achieve as fast an implementation as possible. For this reason, and since the design involves mainly control circuitry, we have from the start chosen to use two phase signaling. We concentrated on the explanation of the asynchronous design issues and the intuition of the implementation rather than on formal techniques. During the whole design path, reflections are given on alternative approaches for the specification of the problem (the high-level communication behaviors) as well as on alternative implementations at the lower levels. This led in particular to two distinct implementations which are discussed and compared. Both of them are asynchronous, but not strictly delay-insensitive since the relative delays in the networks have been taken into account to derive faster implementations in terms of networks of basic components and to use the fastest implementations of these basic components that are allowed by the relative delays. The high-level design given by the communication behaviors of the cop and the stage components allows as much freedom as possible in the sense that instructions and results can flow independently through the pipeline with the sole restrictions that they are not allowed to overtake each other or to swap stages. As a result, this specification allows a stage to be involved simultaneously in a communication with the stage above and in a communication with the stage below. This aspect is particularly exploited by the …